4164 Class RAM Chip - 128cycle/2ms Type - Additional Information
The text block below is from the Internet. Reading that suggests that Z80 based systems that rely only on the Z80's R register (restricted to 128 rows) to control the addressing of the row to be refreshed, will require 4164s of the 128cycle/2ms type.
In early versions of the Z80, the ubiquity of 16 kB RAM chips (i.e. having 128 rows) and something of a lack of foresight resulted in the R register only incrementing over a 7 bit-wide range (0–127, i.e. 128 rows); the 8th bit could be set by the user, but would be left unchanged by the internal cycling. With the rapid advent of 64 kbit+ DRAM chips (with an 8 bit RAS), extra circuitry or logic had to be built around the refresh signal to synthesize the missing 8th bit and prevent blocks of memory being lost after a few milliseconds. In some contexts, it was possible to utilise interrupts to flip the 8th bit at the appropriate time and thus cover the entire range of the R register (256 rows).
Another method, perhaps more universal but also more complex in terms of hardware, was to use an 8-bit counter chip, whose output would provide the refresh RAS address instead of the R register: the refresh signal from the CPU was used as the clock for this counter, resulting in the memory row to be refreshed being incremented with each refresh cycle. Later versions and licensed "work-alikes" of the Z80 core remedied the non-inclusion of the 8th bit in automatic cycling, and modern CPUs have greatly expanded on such basic provisioning to provide rich all-in-one solutions for DRAM refresh.