First Code |
Second Code |
Third Code |
Bit in SIMM at fault |
---|---|---|---|
DD | 00 | none | One (or possibly both) of the two parity bits |
DD | 00 | 01 | Bit 0. Per here, bit 0 is provided by SIMM S1. |
DD | 00 | 02 | Bit 1. Per here, bit 1 is provided by SIMM S1. |
DD | 00 | 04 | Bit 2. Per here, bit 2 is provided by SIMM S1. |
DD | 00 | 08 | Bit 3. Per here, bit 3 is provided by SIMM S1. |
DD | 00 | 10 | Bit 4. Per here, bit 4 is provided by SIMM S1. |
DD | 00 | 20 | Bit 5. Per here, bit 5 is provided by SIMM S1. |
DD | 00 | 40 | Bit 6. Per here, bit 6 is provided by SIMM S1. |
DD | 00 | 80 | Bit 7. Per here, bit 7 is provided by SIMM S1. |
DD | 01 | 00 | Bit 8. Per here, bit 8 is provided by SIMM S2. |
DD | 02 | 00 | Bit 9. Per here, bit 9 is provided by SIMM S2. |
DD | 04 | 00 | Bit 10. Per here, bit 10 is provided by SIMM S2. |
DD | 08 | 00 | Bit 11. Per here, bit 11 is provided by SIMM S2. |
DD | 10 | 00 | Bit 12. Per here, bit 12 is provided by SIMM S2. |
DD | 20 | 00 | Bit 13. Per here, bit 13 is provided by SIMM S2. |
DD | 40 | 00 | Bit 14. Per here, bit 14 is provided by SIMM S2. |
DD | 80 | 00 | Bit 15. Per here, bit 15 is provided by SIMM S2. |