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= POST configures pin as an input | |
= POST configures pin as an output | |
= POST initially configures pin as an output, but near the end of the POST, reconfigures pin as an input |
Note 1 | When PB2 is low, PC0 corresponds to switch 5 within switch block SW2. Because of the way the circuitry is wired, when PB2 is low, pins PC1, PC2 and PC3, will always read high. |
Note 2 | The '8255A I/O Bit Map' table in the 5160 Technical Reference includes "Diagnostic outputs" against port A. That will be a reference to 'checkpoints' that the 5160's POST sends to port A. More information on that is in note 15 at the bottom of here. |
Note 3 | The '8255A I/O Bit Map' table in the 5160 Technical Reference lists the usage of PB2 as 'Spare'. The motherboard circuit diagram shows PB2 connected to jumper pad E5. Per here, jumper pad E5 is part of the keyboard circuitry. Pins 2 and 3 of E5 are normally connected, as seen by the wide PCB trace in the photos at here. Should someone (?) decide to cut that trace, followed by connecting pins 1 and 2 together, then pin PB2 of the 8255 chip will control (via chip U85) the data line of the keyboard connector. At one time, IBM must have seen reason to allow that. But, with jumper pad E5 wired as default, pin PB2 of the 8255 is unused ('spare'), free for custom use - see here. |
Note 4 | The motherboard's POST uses PB6 to momentarily pull the keyboard clock line to LOW, to signal to the keyboard that the keyboard is to do a self-test. In response, the keyboard does a self-test and then sends an AA byte to the 5160 motherboard. See here. (The keyboard also has the ability to pull the keyboard clock line to LOW.) |