From 481cc62bca9bdf3fd3e7b052945d30754f62ee74 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Sun, 6 Apr 2025 01:59:17 +0200 Subject: [PATCH 474/484] thermal: rockchip: Add support for RK3506 Adapted from BSP. Signed-off-by: Ondrej Jirman --- drivers/thermal/rockchip_thermal.c | 89 ++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c index face844bc29d..12603bcb2bcf 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -96,6 +96,7 @@ struct rockchip_tsadc_chip { void __iomem *reg, enum tshut_polarity p); void (*irq_ack)(void __iomem *reg); void (*control)(void __iomem *reg, bool on); + void (*suspend)(struct regmap *grf, void __iomem *reg); /* Per-sensor methods */ int (*get_temp)(const struct chip_tsadc_table *table, @@ -197,6 +198,7 @@ struct rockchip_thermal_data { #define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24) #define TSADCV3_AUTO_Q_SEL_EN BIT(1) +#define TSADCV3_AUTO_Q_SEL_EN_MASK BIT(17) #define TSADCV2_INT_SRC_EN(chn) BIT(chn) #define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn)) @@ -230,6 +232,9 @@ struct rockchip_thermal_data { #define TSADCV9_PD_MODE (0x10001 << 4) #define TSADCV9_Q_MAX_VAL (0xffff0400 << 0) +#define TSADCV13_AUTO_PERIOD_TIME 2500 /* 2.5ms */ +#define TSADCV13_Q_MAX_VAL 0x3ff /* 10bit 1023 */ + #define GRF_SARADC_TESTBIT 0x0e644 #define GRF_TSADC_TESTBIT_L 0x0e648 #define GRF_TSADC_TESTBIT_H 0x0e64c @@ -240,6 +245,8 @@ struct rockchip_thermal_data { #define PX30_GRF_SOC_CON2 0x0408 +#define RK3506_GRF_TSADC_CON 0x10 + #define RK3568_GRF_TSADC_CON 0x0600 #define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0) #define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1) @@ -259,6 +266,10 @@ struct rockchip_thermal_data { #define GRF_CON_TSADC_CH_INV (0x10001 << 1) +/* -40 to 125 is reliable, outside the range existed unreliability */ +#define MIN_TEMP (-60000) +#define MAX_TEMP (180000) + /** * struct tsadc_table - code to temperature conversion table * @code: the value of adc channel @@ -517,6 +528,17 @@ static const struct tsadc_table rk3399_code_table[] = { {TSADCV3_DATA_MASK, 125000}, }; +static const struct tsadc_table rk3506_code_table[] = { + {0, MIN_TEMP}, + {362, MIN_TEMP}, + {395, -40000}, + {503, 25000}, + {604, 85000}, + {672, 125000}, + {757, MAX_TEMP}, + {TSADCV2_DATA_MASK, MAX_TEMP}, +}; + static const struct tsadc_table rk3568_code_table[] = { {0, -40000}, {1584, -40000}, @@ -883,6 +905,38 @@ static void rk_tsadcv9_initialize(struct regmap *grf, void __iomem *regs, regs + TSADCV2_AUTO_CON); } +static void rk_tsadcv13_initialize(struct regmap *grf, void __iomem *regs, + enum tshut_polarity tshut_polarity) +{ + regmap_write(grf, RK3506_GRF_TSADC_CON, RV1106_VOGRF_TSADC_TSEN); + udelay(10); + regmap_write(grf, RK3506_GRF_TSADC_CON, RV1106_VOGRF_TSADC_ANA); + udelay(100); + + writel_relaxed(TSADCV13_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD); + writel_relaxed(TSADCV13_AUTO_PERIOD_TIME, + regs + TSADCV3_AUTO_PERIOD_HT); + writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, + regs + TSADCV3_HIGHT_INT_DEBOUNCE); + writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, + regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE); + writel_relaxed(TSADCV13_Q_MAX_VAL, regs + TSADCV9_Q_MAX); + if (tshut_polarity == TSHUT_HIGH_ACTIVE) + writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH | + TSADCV2_AUTO_TSHUT_POLARITY_MASK, + regs + TSADCV2_AUTO_CON); + else + writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK, + regs + TSADCV2_AUTO_CON); + writel_relaxed(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK, + regs + TSADCV2_AUTO_CON); +} + +static void rk3506_tsadc_suspend(struct regmap *grf, void __iomem *regs) +{ + regmap_write(grf, RK3506_GRF_TSADC_CON, RV1106_VOGRF_TSADC_TSEN & 0xffff0000); +} + static void rk_tsadcv2_irq_ack(void __iomem *regs) { u32 val; @@ -1348,6 +1402,34 @@ static const struct rockchip_tsadc_chip rk3399_tsadc_data = { }, }; +static const struct rockchip_tsadc_chip rk3506_tsadc_data = { + /* cpu */ + .chn_offset = 0, + .chn_num = 1, + + .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ + .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ + .tshut_temp = 95000, + + .initialize = rk_tsadcv13_initialize, + .suspend = rk3506_tsadc_suspend, + .irq_ack = rk_tsadcv4_irq_ack, + .control = rk_tsadcv4_control, + .get_temp = rk_tsadcv4_get_temp, + .set_alarm_temp = rk_tsadcv3_alarm_temp, + .set_tshut_temp = rk_tsadcv3_tshut_temp, + .set_tshut_mode = rk_tsadcv4_tshut_mode, + //.get_trim_code = rk_tsadcv2_get_trim_code, + //.trim_slope = 594, + + .table = { + .id = rk3506_code_table, + .length = ARRAY_SIZE(rk3506_code_table), + .data_mask = TSADCV3_DATA_MASK, + .mode = ADC_INCREMENT, + }, +}; + static const struct rockchip_tsadc_chip rk3568_tsadc_data = { /* cpu, gpu */ .chn_offset = 0, @@ -1431,6 +1513,10 @@ static const struct of_device_id of_rockchip_thermal_match[] = { .compatible = "rockchip,rk3399-tsadc", .data = (void *)&rk3399_tsadc_data, }, + { + .compatible = "rockchip,rk3506-tsadc", + .data = (void *)&rk3506_tsadc_data, + }, { .compatible = "rockchip,rk3568-tsadc", .data = (void *)&rk3568_tsadc_data, @@ -1720,6 +1806,9 @@ static int __maybe_unused rockchip_thermal_suspend(struct device *dev) thermal->chip->control(thermal->regs, false); + if (thermal->chip->suspend) + thermal->chip->suspend(thermal->grf, thermal->regs); + clk_disable(thermal->pclk); clk_disable(thermal->clk); -- 2.49.0