From 23f2a1ee6e662e205c635df6d7e95cf92c7a03b3 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Sun, 21 May 2023 01:42:25 +0200 Subject: [PATCH 410/484] arm64: dts: rk3399-pinephone-pro: Pre-configure DMC This enables dynamic DRAM reclocking. The node needs to be okayed by U-Boot/firmware combo known to support it. Do not enable &dmc by default. Signed-off-by: Ondrej Jirman --- .../dts/rockchip/rk3399-pinephone-pro.dts | 33 +++++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3399-t.dtsi | 29 ++++++++++++++++ 2 files changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts index 351ee2049ad4..9631a73f1912 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts @@ -555,6 +555,39 @@ phys = <&tcphy0_dp>; }; +&dfi { + status = "okay"; +}; + +&dmc { + // This node can only be enabled by FDT patching from U-Boot that + // uses Rockchip TPL/TF-A. DMC only works with the downstream firmware. + // If you enabled this on mainline, your phone will lock up on boot. + //status = "okay"; + + center-supply = <&vdd_center>; + + rockchip,pd-idle-ns = <160>; + rockchip,sr-idle-ns = <10240>; + rockchip,sr-mc-gate-idle-ns = <40960>; + rockchip,srpd-lite-idle-ns = <61440>; + rockchip,standby-idle-ns = <81920>; + + rockchip,lpddr4_odt_dis_freq = <666000000>; + + rockchip,srpd-lite-idle-dis-freq-hz = <0>; + rockchip,standby-idle-dis-freq-hz = <928000000>; + rockchip,sr-mc-gate-idle-dis-freq-hz = <800000000>; + rockchip,pd-idle-dis-freq-hz = <800000000>; + rockchip,sr-idle-dis-freq-hz = <800000000>; +}; + +&dmc_opp_table { + opp00 { + opp-suspend; + }; +}; + &emmc_phy { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-t.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-t.dtsi index 72989f03fcb1..20a9c1ce383d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-t.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-t.dtsi @@ -85,6 +85,31 @@ opp-microvolt = <975000 975000 1150000>; }; }; + + dmc_opp_table: opp-table-3 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <328000000>; + opp-microvolt = <900000>; + }; + opp01 { + opp-hz = /bits/ 64 <416000000>; + opp-microvolt = <900000>; + }; + opp02 { + opp-hz = /bits/ 64 <666000000>; + opp-microvolt = <900000>; + }; + opp03 { + opp-hz = /bits/ 64 <856000000>; + opp-microvolt = <900000>; + }; + opp04 { + opp-hz = /bits/ 64 <928000000>; + opp-microvolt = <925000>; + }; + }; }; &cpu_l0 { @@ -111,6 +136,10 @@ operating-points-v2 = <&cluster1_opp>; }; +&dmc { + operating-points-v2 = <&dmc_opp_table>; +}; + &gpu { operating-points-v2 = <&gpu_opp_table>; }; -- 2.49.0