From c862de86f47648b18c766186296d18e5af5081bc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= Date: Mon, 14 Aug 2023 07:28:11 +0200 Subject: [PATCH 275/484] clk: sunxi-ng: sun50i-a64: Switch parent of MIPI-DSI to periph0(1x) This makes video0(1x) clock less constrained, and improves compatibility with external monitors on Pinephone when using both internal display and HDMI output at once. Signed-off-by: Ondrej Jirman --- drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c index 7463362ea45f..bcded4e1db5f 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c @@ -942,6 +942,8 @@ static struct ccu_mux_nb sun50i_a64_cpu_nb = { .bypass_index = 1, /* index of 24 MHz oscillator */ }; +#define CCU_MIPI_DSI_CLK 0x168 + static int sun50i_a64_ccu_probe(struct platform_device *pdev) { void __iomem *reg; @@ -958,9 +960,16 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev) writel(val | (0 << 16), reg + SUN50I_A64_PLL_AUDIO_REG); ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &val); - if (ret) + if (ret) { writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG); + /* Set MIPI-DSI clock parent to periph0(1x), so that video0(1x) is free to change. */ + val = readl(reg + CCU_MIPI_DSI_CLK); + val &= 0x30f; + val |= (2 << 8) | ((4 - 1) << 0); /* M-1 */ + writel(val, reg + CCU_MIPI_DSI_CLK); + } + ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a64_ccu_desc); if (ret) return ret; -- 2.49.0