From 4bb0a14a32e9760ba5eedd1dc417b410c6cdf063 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Tue, 25 Jun 2024 00:00:14 +0200 Subject: [PATCH 463/480] thermal: rockchip: Add support for RV1106 SoC This SoC includes a thermal sensor, which can be supported by this driver. Add support for it. Signed-off-by: Ondrej Jirman --- drivers/thermal/rockchip_thermal.c | 93 ++++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c index f551df48eef9..db961dc1168f 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -185,6 +185,8 @@ struct rockchip_thermal_data { #define TSADCV2_AUTO_PERIOD_HT 0x6c #define TSADCV3_AUTO_PERIOD 0x154 #define TSADCV3_AUTO_PERIOD_HT 0x158 +#define TSADCV9_Q_MAX 0x210 +#define TSADCV9_FLOW_CON 0x218 #define TSADCV2_AUTO_EN BIT(0) #define TSADCV2_AUTO_EN_MASK BIT(16) @@ -224,10 +226,18 @@ struct rockchip_thermal_data { #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */ +#define TSADCV9_AUTO_SRC (0x10001 << 0) +#define TSADCV9_PD_MODE (0x10001 << 4) +#define TSADCV9_Q_MAX_VAL (0xffff0400 << 0) + #define GRF_SARADC_TESTBIT 0x0e644 #define GRF_TSADC_TESTBIT_L 0x0e648 #define GRF_TSADC_TESTBIT_H 0x0e64c +#define RV1106_VOGRF_TSADC_CON 0x6000C +#define RV1106_VOGRF_TSADC_TSEN (0x10001 << 8) +#define RV1106_VOGRF_TSADC_ANA (0xff0007 << 0) + #define PX30_GRF_SOC_CON2 0x0408 #define RK3568_GRF_TSADC_CON 0x0600 @@ -264,6 +274,15 @@ struct tsadc_table { int temp; }; +static const struct tsadc_table rv1106_code_table[] = { + {0, -40000}, + {396, -40000}, + {504, 25000}, + {605, 85000}, + {673, 125000}, + {TSADCV2_DATA_MASK, 125000}, +}; + static const struct tsadc_table rv1108_table[] = { {0, -40000}, {374, -40000}, @@ -834,6 +853,35 @@ static void rk_tsadcv8_initialize(struct regmap *grf, void __iomem *regs, regs + TSADCV2_AUTO_CON); } +static void rk_tsadcv9_initialize(struct regmap *grf, void __iomem *regs, + enum tshut_polarity tshut_polarity) +{ + regmap_write(grf, RV1106_VOGRF_TSADC_CON, RV1106_VOGRF_TSADC_TSEN); + udelay(10); + regmap_write(grf, RV1106_VOGRF_TSADC_CON, RV1106_VOGRF_TSADC_ANA); + udelay(100); + + writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD); + writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, + regs + TSADCV3_AUTO_PERIOD_HT); + writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, + regs + TSADCV3_HIGHT_INT_DEBOUNCE); + writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, + regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE); + writel_relaxed(TSADCV9_AUTO_SRC, regs + TSADCV2_INT_PD); + writel_relaxed(TSADCV9_PD_MODE, regs + TSADCV9_FLOW_CON); + writel_relaxed(TSADCV9_Q_MAX_VAL, regs + TSADCV9_Q_MAX); + if (tshut_polarity == TSHUT_HIGH_ACTIVE) + writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH | + TSADCV2_AUTO_TSHUT_POLARITY_MASK, + regs + TSADCV2_AUTO_CON); + else + writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK, + regs + TSADCV2_AUTO_CON); + writel_relaxed(TSADCV3_AUTO_Q_SEL_EN | (TSADCV3_AUTO_Q_SEL_EN << 16), + regs + TSADCV2_AUTO_CON); +} + static void rk_tsadcv2_irq_ack(void __iomem *regs) { u32 val; @@ -1060,6 +1108,22 @@ static void rk_tsadcv3_tshut_mode(int chn, void __iomem *regs, writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN); } +static void rk_tsadcv4_tshut_mode(int chn, void __iomem *regs, + enum tshut_mode mode) +{ + u32 val_gpio, val_cru; + + if (mode == TSHUT_MODE_GPIO) { + val_gpio = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn); + val_cru = TSADCV2_INT_SRC_EN_MASK(chn); + } else { + val_cru = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn); + val_gpio = TSADCV2_INT_SRC_EN_MASK(chn); + } + writel_relaxed(val_gpio, regs + TSADCV3_HSHUT_GPIO_INT_EN); + writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN); +} + static const struct rockchip_tsadc_chip px30_tsadc_data = { /* cpu, gpu */ .chn_offset = 0, @@ -1084,6 +1148,31 @@ static const struct rockchip_tsadc_chip px30_tsadc_data = { }, }; +static const struct rockchip_tsadc_chip rv1106_tsadc_data = { + /* cpu */ + .chn_offset = 0, + .chn_num = 1, + + .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ + .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ + .tshut_temp = 95000, + + .initialize = rk_tsadcv9_initialize, + .irq_ack = rk_tsadcv4_irq_ack, + .control = rk_tsadcv4_control, + .get_temp = rk_tsadcv4_get_temp, + .set_alarm_temp = rk_tsadcv3_alarm_temp, + .set_tshut_temp = rk_tsadcv3_tshut_temp, + .set_tshut_mode = rk_tsadcv4_tshut_mode, + + .table = { + .id = rv1106_code_table, + .length = ARRAY_SIZE(rv1106_code_table), + .data_mask = TSADCV2_DATA_MASK, + .mode = ADC_INCREMENT, + }, +}; + static const struct rockchip_tsadc_chip rv1108_tsadc_data = { /* cpu */ .chn_offset = 0, @@ -1309,6 +1398,10 @@ static const struct of_device_id of_rockchip_thermal_match[] = { { .compatible = "rockchip,px30-tsadc", .data = (void *)&px30_tsadc_data, }, + { + .compatible = "rockchip,rv1106-tsadc", + .data = (void *)&rv1106_tsadc_data, + }, { .compatible = "rockchip,rv1108-tsadc", .data = (void *)&rv1108_tsadc_data, -- 2.49.0