From 89dcfdac3dda1e135c6c1fcb3d3e0b55829414af Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Fri, 21 Jun 2024 01:41:46 +0200 Subject: [PATCH 460/480] pinctrl: rockchip: Add support for RV1106/RV1103 Forward ported modifications from Rockchip BSP. There's no public datasheet. Signed-off-by: Ondrej Jirman --- drivers/pinctrl/pinctrl-rockchip.c | 207 +++++++++++++++++++++++++++++ drivers/pinctrl/pinctrl-rockchip.h | 1 + 2 files changed, 208 insertions(+) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 15145882950f..bacc37d9f230 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -1429,6 +1429,166 @@ static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, return 0; } +#define RV1106_DRV_BITS_PER_PIN 8 +#define RV1106_DRV_PINS_PER_REG 2 +#define RV1106_DRV_GPIO0_OFFSET 0x10 +#define RV1106_DRV_GPIO1_OFFSET 0x80 +#define RV1106_DRV_GPIO2_OFFSET 0x100C0 +#define RV1106_DRV_GPIO3_OFFSET 0x20100 +#define RV1106_DRV_GPIO4_OFFSET 0x30020 + +static int rv1106_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + /* GPIO0_IOC is located in PMU */ + switch (bank->bank_num) { + case 0: + *regmap = info->regmap_pmu; + *reg = RV1106_DRV_GPIO0_OFFSET; + break; + + case 1: + *regmap = info->regmap_base; + *reg = RV1106_DRV_GPIO1_OFFSET; + break; + + case 2: + *regmap = info->regmap_base; + *reg = RV1106_DRV_GPIO2_OFFSET; + break; + + case 3: + *regmap = info->regmap_base; + *reg = RV1106_DRV_GPIO3_OFFSET; + break; + + case 4: + *regmap = info->regmap_base; + *reg = RV1106_DRV_GPIO4_OFFSET; + break; + + default: + dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); + break; + } + + *reg += ((pin_num / RV1106_DRV_PINS_PER_REG) * 4); + *bit = pin_num % RV1106_DRV_PINS_PER_REG; + *bit *= RV1106_DRV_BITS_PER_PIN; + + return 0; +} + +#define RV1106_PULL_BITS_PER_PIN 2 +#define RV1106_PULL_PINS_PER_REG 8 +#define RV1106_PULL_GPIO0_OFFSET 0x38 +#define RV1106_PULL_GPIO1_OFFSET 0x1C0 +#define RV1106_PULL_GPIO2_OFFSET 0x101D0 +#define RV1106_PULL_GPIO3_OFFSET 0x201E0 +#define RV1106_PULL_GPIO4_OFFSET 0x30070 + +static int rv1106_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + /* GPIO0_IOC is located in PMU */ + switch (bank->bank_num) { + case 0: + *regmap = info->regmap_pmu; + *reg = RV1106_PULL_GPIO0_OFFSET; + break; + + case 1: + *regmap = info->regmap_base; + *reg = RV1106_PULL_GPIO1_OFFSET; + break; + + case 2: + *regmap = info->regmap_base; + *reg = RV1106_PULL_GPIO2_OFFSET; + break; + + case 3: + *regmap = info->regmap_base; + *reg = RV1106_PULL_GPIO3_OFFSET; + break; + + case 4: + *regmap = info->regmap_base; + *reg = RV1106_PULL_GPIO4_OFFSET; + break; + + default: + dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); + break; + } + + *reg += ((pin_num / RV1106_PULL_PINS_PER_REG) * 4); + *bit = pin_num % RV1106_PULL_PINS_PER_REG; + *bit *= RV1106_PULL_BITS_PER_PIN; + + return 0; +} + +#define RV1106_SMT_BITS_PER_PIN 1 +#define RV1106_SMT_PINS_PER_REG 8 +#define RV1106_SMT_GPIO0_OFFSET 0x40 +#define RV1106_SMT_GPIO1_OFFSET 0x280 +#define RV1106_SMT_GPIO2_OFFSET 0x10290 +#define RV1106_SMT_GPIO3_OFFSET 0x202A0 +#define RV1106_SMT_GPIO4_OFFSET 0x300A0 + +static int rv1106_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + /* GPIO0_IOC is located in PMU */ + switch (bank->bank_num) { + case 0: + *regmap = info->regmap_pmu; + *reg = RV1106_SMT_GPIO0_OFFSET; + break; + + case 1: + *regmap = info->regmap_base; + *reg = RV1106_SMT_GPIO1_OFFSET; + break; + + case 2: + *regmap = info->regmap_base; + *reg = RV1106_SMT_GPIO2_OFFSET; + break; + + case 3: + *regmap = info->regmap_base; + *reg = RV1106_SMT_GPIO3_OFFSET; + break; + + case 4: + *regmap = info->regmap_base; + *reg = RV1106_SMT_GPIO4_OFFSET; + break; + + default: + dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); + break; + } + + *reg += ((pin_num / RV1106_SMT_PINS_PER_REG) * 4); + *bit = pin_num % RV1106_SMT_PINS_PER_REG; + *bit *= RV1106_SMT_BITS_PER_PIN; + + return 0; +} + #define RV1108_PULL_PMU_OFFSET 0x10 #define RV1108_PULL_OFFSET 0x110 #define RV1108_PULL_PINS_PER_REG 8 @@ -2778,6 +2938,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT : PIN_CONFIG_BIAS_DISABLE; case PX30: + case RV1106: case RV1108: case RK3188: case RK3288: @@ -2838,6 +2999,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, ret = regmap_write(regmap, reg, data); break; case PX30: + case RV1106: case RV1108: case RV1126: case RK3188: @@ -3107,6 +3269,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, case RK3066B: return pull ? false : true; case PX30: + case RV1106: case RV1108: case RV1126: case RK3188: @@ -3848,6 +4011,48 @@ static struct rockchip_pin_ctrl px30_pin_ctrl = { .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, }; +static struct rockchip_pin_bank rv1106_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", + IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, + IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, + IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, + IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU), + PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0, 0x08, 0x10, 0x18), + PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x10020, 0x10028, 0, 0), + PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x20040, 0x20048, 0x20050, 0x20058), + PIN_BANK_IOMUX_FLAGS_OFFSET(4, 24, "gpio4", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0, + 0x30000, 0x30008, 0x30010, 0), +}; + +static struct rockchip_pin_ctrl rv1106_pin_ctrl __maybe_unused = { + .pin_banks = rv1106_pin_banks, + .nr_banks = ARRAY_SIZE(rv1106_pin_banks), + .label = "RV1106-GPIO", + .type = RV1106, + .pull_calc_reg = rv1106_calc_pull_reg_and_bit, + .drv_calc_reg = rv1106_calc_drv_reg_and_bit, + .schmitt_calc_reg = rv1106_calc_schmitt_reg_and_bit, +}; + static struct rockchip_pin_bank rv1108_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, IOMUX_SOURCE_PMU, @@ -4376,6 +4581,8 @@ static struct rockchip_pin_ctrl rk3588_pin_ctrl = { static const struct of_device_id rockchip_pinctrl_dt_match[] = { { .compatible = "rockchip,px30-pinctrl", .data = &px30_pin_ctrl }, + { .compatible = "rockchip,rv1106-pinctrl", + .data = &rv1106_pin_ctrl }, { .compatible = "rockchip,rv1108-pinctrl", .data = &rv1108_pin_ctrl }, { .compatible = "rockchip,rv1126-pinctrl", diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h index 87a20cec8e21..1ee8a3481a65 100644 --- a/drivers/pinctrl/pinctrl-rockchip.h +++ b/drivers/pinctrl/pinctrl-rockchip.h @@ -185,6 +185,7 @@ enum rockchip_pinctrl_type { PX30, + RV1106, RV1108, RV1126, RK2928, -- 2.49.0