From 0dd0640745a8f4c85b15a083939efecbfab9813d Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megi@xff.cz>
Date: Mon, 29 Apr 2024 13:57:52 +0200
Subject: [PATCH 092/480] dt-bindings: Add Zynq clocks

So that we don't have to remember magic numbers.

Signed-off-by: Ondrej Jirman <megi@xff.cz>
---
 arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts |  2 +
 include/dt-bindings/clock/xlnx-zynq-clk.h  | 60 ++++++++++++++++++++++
 2 files changed, 62 insertions(+)
 create mode 100644 include/dt-bindings/clock/xlnx-zynq-clk.h

diff --git a/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts b/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts
index 53fa6dbfd8fd..aa47b907895e 100644
--- a/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts
+++ b/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts
@@ -5,6 +5,8 @@
 /dts-v1/;
 /include/ "zynq-7000.dtsi"
 
+#include "dt-bindings/clock/xlnx-zynq-clk.h"
+
 / {
 	model = "Ebang EBAZ4205";
 	compatible = "ebang,ebaz4205", "xlnx,zynq-7000";
diff --git a/include/dt-bindings/clock/xlnx-zynq-clk.h b/include/dt-bindings/clock/xlnx-zynq-clk.h
new file mode 100644
index 000000000000..4cbf58232f15
--- /dev/null
+++ b/include/dt-bindings/clock/xlnx-zynq-clk.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Xilinx Zynq Clocks
+ *
+ *  Copyright (C) 2024 Ondrej Jirman <megi@xff.cz>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ZYNQ_H
+#define _DT_BINDINGS_CLK_ZYNQ_H
+
+#define CLK_ARMPLL        0
+#define CLK_DDRPLL        1
+#define CLK_IOPLL	  2
+#define CLK_CPU_6OR4X     3
+#define CLK_CPU_3OR2X     4
+#define CLK_CPU_2X        5
+#define CLK_CPU_1X        6
+#define CLK_DDR2X         7
+#define CLK_DDR3X         8
+#define CLK_DCI           9
+#define CLK_LQSPI         10
+#define CLK_SMC           11
+#define CLK_PCAP          12
+#define CLK_GEM0          13
+#define CLK_GEM1          14
+#define CLK_FCLK0         15
+#define CLK_FCLK1         16
+#define CLK_FCLK2         17
+#define CLK_FCLK3         18
+#define CLK_CAN0          19
+#define CLK_CAN1          20
+#define CLK_SDIO0         21
+#define CLK_SDIO1         22
+#define CLK_UART0         23
+#define CLK_UART1         24
+#define CLK_SPI0          25
+#define CLK_SPI1          26
+#define CLK_DMA           27
+#define CLK_USB0_APER     28
+#define CLK_USB1_APER     29
+#define CLK_GEM0_APER     30
+#define CLK_GEM1_APER     31
+#define CLK_SDIO0_APER    32
+#define CLK_SDIO1_APER    33
+#define CLK_SPI0_APER     34
+#define CLK_SPI1_APER     35
+#define CLK_CAN0_APER     36
+#define CLK_CAN1_APER     37
+#define CLK_I2C0_APER     38
+#define CLK_I2C1_APER     39
+#define CLK_UART0_APER    40
+#define CLK_UART1_APER    41
+#define CLK_GPIO_APER     42
+#define CLK_LQSPI_APER    43
+#define CLK_SMC_APER      44
+#define CLK_SWDT          45
+#define CLK_DBG_TRC       46
+#define CLK_DBG_APB       47
+
+#endif
-- 
2.49.0